User Circuit

Supports synchronous logic circuits.

All input signals automatically sampled, synchronized to the clock and hardened against metastability.

All output signals automatically registered.

Your circuit may consist of low level elements such as gates and flip-flops, and also state machines and higher level functions defined from the foregoing. The higher level functions can range from simple counters to highly complex sub-systems.

I/O Terminals are assigned to pins directly on the Top Level Schematic of your design. While monitoring the circuit, an I/O Terminal shows the active pin value as a 1 or 0 on the left hand side of the symbol, and on the right hand side the number represents whether or not the terminal has been forced high or low.

Design Capture

Integrated project-orientated environment handles files transparently.

Project tree displays multi-level project structure as appropriate for both online and offline use.

Circuits are entered as schematics and state diagrams organized on the project tree.

Built in library of basic components.

Multi-level schematics supported to any level of nesting.

Sub-schematics represented as automatically generated customizable symbols on the levels above.

Support for drilling down to any lower level from the top level to reveal detailed circuit structure by double-clicking on sub-schematic symbols.

Auto-router assisted wire placement with rubber-banding.

I/O terminals addressed in terms of Logic Module header pins, not FPGA pins.

Environment has customizable toolbars that can be docked or floated.

Schematics may be annotated with text and graphics.

Version Manager automatically saves a new version each compile-time. User may revert to any previous version and start a new development branch at that point.

Defining the initial value of RAMs is easy using Interactive Logic, simply enter the values as hex in the properties dialog of the component instance.

Symbol Editor

Allows automatically generated symbol graphics for sub-schematics to be fully customized.

Allows data from any level within a symbol’s sub-schematics to be displayed on the symbol.

Symbols for your schematics are created automatically, but you can edit the symbols and even add data viewers from any component within the schematic onto the symbol. In this image we have added a counters value to the schematics symbol so we can monitor it while online.

Compilation

Simplified one button circuit compilation using Xilinx compiler.

Automatically presented error and warning reports simplified and adjusted to suit Interactive Logic environment. Full reports available via menus.

All necessary parameters to control compilation and fit it to the Logic Module handled automatically.

Configuration download

One button operation, fast download via TCP/IP.

Reconfiguration with modified design without disturbing data in parts of circuit that remain unchanged.

Write Program to Flash function provides for circuit configuration and run at power-on with or without a Comms Card fitted.

Clock Control

Once downloaded, circuit may be single-stepped, or run continuously. Starting and stopping is glitch-free and the circuit state is correctly maintained for examination and restarting.

Breakpoints stop operation prior to next clock edge.

Clock frequency may be set between 10MHz and 100MHz. 86 choices available. Gap between adjacent values of 2 to 4% of value.

Circuit data display

Circuit state data displayed on schematics and state diagrams while the circuit is both running and stopped.

Data may be seen to change and states to progress.

All data displayed is read from the FPGA circuit. None is the result of simulation.

Flip-flops and counters, etc, display data on their symbols.

Signal levels may be displayed with Signal Taps.

User schematic symbols display data from underlying schematics as defined by user.

Circuit data modification and control

User may modify circuit state data while the circuit is running or stopped.

Individual bits may be clicked (or double-clicked) to toggle their value. Multi-bit values are modified via a dialog.

Input and output terminals may have their values forced to ‘1’ or ‘0’, or allowed to maintain their natural levels.

Any other signal may be controlled in a similar manner using Forceable buffers.

Outputs may be disabled (set to high impedance) during both Run and Pause, during Pause only, or left to assume their natural circuit levels during both Run and Pause.

Emergency Stop provides for rapid output disabling.

Here we are modifying the value of an 8 bit counter simply by double-clicking on the displayed value and entering a new value.

Data Display

Digital waveform style display of Data vs. Clock Cycles.

Data from any schematic level and component instance may be displayed.

Data is gathered each clock cycle during single-stepping or slow operation of the circuit.

Ideal for detailed debugging of circuits during development.

Data displayable as composite or bit values.

Two markers that can snap to transitions allow distance between edges to be determined as a clock count.

Display may be zoomed over a wide range.

Waveforms may be saved and redisplayed later when offline.

Waveforms may be printed.

Online set-ups automatically saved across intervals offline.

Signal Display

Digital waveform style display of Signals vs. Time.

Can display any signal from any schematic level while circuit is running.

Minimal dead-time suits monitoring over periods of continuous uninterrupted operation up to 7 days.

Only causes circuit interruption when rising or falling edge events occur on monitored signals, otherwise circuit operation is full speed.

Signals displayable as bit values.

Two markers that can snap to transitions allow distance between edges to be determined as a clock count and equivalent time.

Display may be zoomed over a wide range.

Waveforms may be saved and redisplayed later when offline.

Waveforms may be printed.

Graphics rendering may be disabled until after signal capture to minimize dead-time.

Online set-ups automatically saved across intervals offline.

Log records clock cycles at which signal edges occur.

Breakpoints

Breakpoints may be set on up to 39 signals at any one time.

Trigger signals may be from any schematic level and component instance.

Trigger edges may be rising, or falling.

Breakpoints may be separately enabled and disabled or used in conjunction with Signal Display.

Circuit operation stops prior to next clock edge. (May not apply at high frequencies.)

Running circuit up to a breakpoint with Disconnect and Run allows full speed uninterrupted circuit operation until the break condition is met. Saving signal states in shift registers for unloading after the break occurs allows signal states leading up to the breakpoint to be displayed.

Log records clock cycle at which breakpoint occurs.

Data collection during uninterrupted operation

You can display signal states associated with a fault occurring during full speed operation by -

running the circuit with Run unmonitored at full speed until a fault associated breakpoint is triggered,

saving the signal states in shift registers, and

unloading the shift registers after the break occurs.

Saving and displaying the signal causing the break will allow you to easily see the timing involved.

Frequency testing

Frequency Testing, combined with Behavioral Testing performed with the other tools described, replaces the behavioral and timing simulation used in conventional FPGA design methodology.

Fully discussed in Determining Clock Frequency.

Provides for testing your circuit to determine the maximum allowable frequency for error free operation.

Supports automatic recording of test stimuli input and handling of files.

Supports automated test runs, which include multiple individual tests.

Suited to one off and low volume applications.

Translates tests from earlier circuit versions.

Provides for editing tests, and displaying data occurring during test runs as waveforms.

PC Applications Library

Allows programs written for a PC to access a Logic Module while it is running or stopped.

Supports C++, C# and Java languages.

Convenient library items are generated specific to the circuit you have designed.

Data is accessed in terms of the names you allocate to it. Names used by the library default to the names on the schematics if those names comply with language requirements.