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Logic Module Specifications
Interactive Logic Module
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User Circuit
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Supports customer-defined synchronous logic circuits.
All input signals automatically sampled, synchronized to the clock and
hardened against metastability.
All output signals automatically registered.
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FPGA
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Manufacturer
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Xilinx
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Type
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XC2S200E-6PQ208C
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Flip-flops available
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more than 5000
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Four-input combinational logic function resources
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more than 5000
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Programming cycles
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unlimited
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Timing1
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I/O setup and hold time
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1.9 / 0ns
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Clock pad to output time2
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6.6ns
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Minimum leeway allowed for metastable settling3
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5ns
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Flash ROM
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Programming cycles
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1000 minimum
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(Only required for saving circuit configuration for power-up configuration
and run)
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Clock frequencies selectable
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Minimum
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10MHz
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Maximum
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100MHz
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Number of discrete values
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86
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Gap between adjacent frequencies
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2 to 4% of value
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Power Supply Required
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Voltage including deviations due to ripple and noise
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+5 Volts DC ±5%
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Current with Comms Card fitted during normal operation4
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0.5A maximum
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Turn-on transient4
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0.7A maximum
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Power cable colours
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+5VDC
0V
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yellow
black
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Operational Timing
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Data Access to User Circuit with200 to 300 flip-flops
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500us typical
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Configuration download
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2s typical
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Power-on configuration
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0.1s typical
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These times assume a 100MHz network where applicable.
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I/O
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I/O available to user
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96
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Pins per header
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20
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Headers
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6
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I/O pins per header
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16
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Ground pins per header
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4
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Ground pin positions
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3, 8, 13, and 18
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Each I/O pin is usable as an input, output or bidirectional
connection
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I/O Drive1
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I/O standard
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LVTTL
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Slew rate
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Slow
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Drive current
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12mA
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I/O drive also suits 3V3 CMOS.
5 Volt tolerance is achievable with proper techniques.
See the Xilinx Answers Database entry Are
Spartan-IIE I/Os 5V-tolerant? and the quoted Xilinx 5
Volt tolerance documents
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I/O Headers
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2 x 10 way unshrouded 2.54mm (0.1”) matrix, 0.64mm
(0.025”) square pins, pin free length 5.84mm (0.230”).
Pins Phosphor-bronze, with 0.76um (30u”) gold over 1.27um (50u”) nickel in
contact area.
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Comms Card Sockets
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Beryllium copper contacts, with 0.76um (30u”) gold over
1.27um (50u”) nickel in contact area.
4 contact points per circuit.
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Operating Temperature Range
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Commercial range.
Call if wider range required.
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0ºC to 70ºC
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Heat sink Temperature
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Absolute Maximum Heatsink Temperature
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110ºC
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Dissipation is dependent on I/O drive and clock
frequency related supply current requirements.
Reliability will be enhanced by running the heat sinks at a significantly
lower temperature.
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Humidity
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Non-condensing
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5%RH to 95%RH
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Note:
1. See Xilinx datasheets for
full information.
2. This is the value for LVTTL. Values are dependent on load capacitance,
interface standard, and selected drive speed. See Xilinx datasheets for
full information
3. See Determining Clock
Frequency.
4. I/O current draw and heavy usage of logic with a high clock frequency
may increase these figures.
Development Comms Card
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Interactive Logic Features Supported
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All.
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Communications
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Standard 10/100Base-T Ethernet LAN.
RJ-45 socket
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Communications Protocol
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TCP/IP
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Communications Parameters
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Set via software
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Cabling
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Standard UTP for 10/100Base-T Ethernet.
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Fixed IP Parameters
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IP Address
Netmask
Gateway
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192.168.0.223
255.255.255.0
192.168.0.1
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Default Customizable IP Parameters
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IP Address
Netmask
Gateway
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10.0.0.223
255.0.0.0
10.0.0.1
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Network Utilization
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Percentage of capacity on 100MHz network
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less than 0.1% typical
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Network Indicator LEDs
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Speed (SPD)
Link (LNK)
Activity (ACT)
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green
green
yellow
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Power Source
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Supplied from Logic Module
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Operating Temperature
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–40°C to +70°C
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Humidity
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5% to 95%, non-condensing
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The high impedance real-time clock area of the Comms
Card has a conformal coating to prevent problems with humidity.
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Monitoring Comms Card
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Interactive Logic Features Supported
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File Menu - all.
Edit Menu - all.
View Menu except Data Display and Signal Display.
Tools Menu - all.
Project Menu except -
Single
and Continuous Step.
Disable
Outputs and Disable Outputs in Pause.
Record
Test Run.
Test
Runs Manager.
Configure
Signal Monitoring.
Schematic Menu - all.
Configuration Menu - all.
Breakpoints are not available.
The Event Log will be viewable but remain empty.
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Other Features
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As per Development Communications Card.
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Dimensions
The drawing shows the main dimensions for a Logic Module
& Comms Card assembly. All dimensions are referenced to horizontal and
vertical baselines that pass through the lower left corner of the Logic Module.
The Logic Module heatsinks reach 30 mm above the PCB
surface, and there should be at least 10mm free space above that to allow
circulation of cooling air. It is recommended that a 2mm clearance be left all
around the complete assembly for air circulation purposes.
Dimensions for Logic Module and Comms Card Assembly.
(Top View)
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Signal/Pin
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X Coordinate
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Y Coordinate
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User I/O Connector JP1 Pin 1
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46.14
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64.96
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User I/O Connector JP2 Pin 1
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74.14
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65.00
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User I/O Connector JP3 Pin 1
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94.46
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60.50
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User I/O Connector JP4 Pin 1
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94.46
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32.39
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User I/O Connector JP5 Pin 1
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97.00
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4.14
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User I/O Connector JP6 Pin 1
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69.00
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4.14
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FPGA Clock Output
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68.84
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52.02
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FPGA Clear Output
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71.38
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54.54
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FPGA User Circuit Run Output
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91.60
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28.50
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5 Volts draw-off point
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35.90
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56.22
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3.3 Volts draw-off point
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35.90
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53.68
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1.8 Volts draw-off point
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35.90
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51.14
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0 Volts draw-off point (Ground)
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35.90
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48.60
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Coordinates of connectors and signal connection points.
(All coordinates are in millimetres.)
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